#!/usr/bin/env python

""" 
CLASS: RTLReg
 - Represent the register for RTL.
"""

__author__ = 'liwei79@gmail.com'

_BASE_REG_START, _BASE_REG_END = 0, 25
TEMP_REG_START = 26

class RTLReg:
    """
    Reg can be constructed by an [a-z] charater or an 
    interger value. 
    For  Example:
        Reg("a")
    and
        Reg(0)
    are equivalent.
    """

    def __init__(self, reg):
	""" reg can be a-z charactor or an integer number """
        if isinstance(reg, str):
            assert(len(reg) == 1 and reg<="z" and reg>="a" 
                and "base reg should be in [a-z]")
            self.type = "BASE_REG"
            self.reg = ord(reg) - ord("a")
        elif isinstance(reg, int):
            if reg >= _BASE_REG_START and reg <= _BASE_REG_END:
                self.type = "BASE_REG"
            else:
                self.type = "TEMP_REG"
            self.reg = reg
        else:
            assert("Invalid register value")

    def getType(self):
        """ To know if a register is "BASE_REG" or "TEMP_REG" """
        return self.type

    def getRegNum(self):
        """  Get the integer number of this register """
        return self.reg

    def getRegName(self):
        """ Get the name of this register """
        if self.type == "BASE_REG":
            return "%s" % chr(self.reg + ord("a"))
        elif self.type == "TEMP_REG":
            return "t%d" % self.reg
        else:
            assert("Unknown reg")

    def __repr__(self): 
        """ Just print the name of the register """
        return self.getRegName()
        

if __name__ == "__main__":
    print RTLReg("a")
    print RTLReg(0)
    print RTLReg("z")
    #print RTLReg("Z") #- Not support uppercase
    print RTLReg(26)
    print RTLReg(27)
    print RTLReg(100)
